1. Field of the Invention
The present invention relates to an oscillator, and more particularly, to an oscillator free from being interfered by a noise signal.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating an oscillator 100 according to the prior art. The conventional oscillator 100 is a ring oscillator with odd numbers of inverters connected in series, and each of the inverters couples between a voltage source VDD (providing a voltage VDD) and a voltage source VSS (providing a voltage VSS) respectively. Voltage source VDD in FIG. 1 is served as a power source while voltage source VSS is served as a ground end (e.g., GND). In addition, the conventional oscillator 100 can further include a buffer B coupled to an output end of the oscillator 100, for receiving a clock signal CLK and buffering clock signal CLK to generate a clock signal CLKB accordingly. Buffer B can be implemented by an amplifier or a comparator. Additionally, In FIG. 1, buffer B is used to enhance signal magnitude of clock signal CLK, thereby generating clock signal CLKB with a stronger driving ability than clock signal CLK, or, adjusting waveform of clock signal CLK to generate clock signal CLKB with a square wave more perfectly. In this way, the improved clock signal CLKB hence is more suitable for follow-up process.
However, oscillator 100 generates clock signal CLK with errors, e.g. phase errors, when noise signals exist on voltage source VDD and/or voltage source VSS.
Please refer to FIG. 2, a diagram illustrating a first condition of clock signal CLK while being interfered by a noise signal carried from the voltage source (i.e., VDD or VSS). As shown in FIG. 2, when the noise signal exists on voltage source VDD or voltage source VSS, clock signal CLK, which originally ought to keep logically high at this time, is changed to be logically low, owing to the interference from the noise signal. In such condition, the clock signals CLK interfered by the noise signal may be unsuitable for use.
Please refer to FIG. 3; a diagram illustrating a second condition of clock signal CLK interfered by the noised signal. As shown in FIG. 3, the dashed line indicates that clock signal CLK should be changed to logically low. However, the noise signal exists on voltage sources VDD/VSS, clock signal CLK, at this time, and hence keeps clock signal CLK logically high rather than logically low. In such condition, clock signal CLK interfered by the noise signal may be insuitable for use as well.